I am a student an have designed and implemented a processor with a completely different architecture than RIS or CISC... More closer to TTA architecture.
I am getting 1440 MIPS at 45 MHz. and 16 instructions per machine cycle....
I want information from you all so as to make it "FOR" AI programming..
It has pretty good level of instruction level parallelism.
1)C macro type instructions... that is same instruction for all data widths
2)"Globally synchronous locally asynchronous" operation which consumes very less power